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| S3C80F7/C80F9/C80G7/C80G9 (KS88C01524/C01532/C01624/C01632) PRODUCT OVERVIEW 1 PRODUCT OVERVIEW S3C8-SERIES MICROCONTROLLERS Samsung's S3C8 series of 8-bit single-chip CMOS microcontrollers offers a fast and efficient CPU, a wide range of integrated peripherals, and various mask-programmable ROM sizes. Important CPU features include: -- Efficient register-oriented architecture -- Selectable CPU clock sources -- Idle and Stop power-down mode release by interrupt -- Built-in basic timer with watchdog function A sophisticated interrupt structure recognizes up to eight interrupt levels. Each level can have one or more interrupt sources and vectors. Fast interrupt processing (within a minimum six CPU clocks) can be assigned to specific interrupt levels. S3C80F7/C80F9/C80G7/C80G9 Microcontroller The S3C80F7/C80F9/C80G7/C80G9 single-chip CMOS microcontroller is fabricated using a highly advanced CMOS process and is based on Samsung's newest CPU architecture. The S3C80F9/C80G9 is the microcontroller which has 32-Kbyte mask-programmable ROM and S3C80F7/C80G7 is the microcontroller which has 24-Kbyte mask-programmable ROM. The S3P80F9/P80G9 is the microcontroller which has 32-Kbyte one-time-programmable EPROM and S3P80F7/P80G7 is the microcontroller which has 24-Kbyte one-time-programmable EPROM. Using a proven modular design approach, Samsung engineers developed S3C80F7/C80F9/C80G7/C80G9 by integrating the following peripheral modules with the powerful SAM87 RC core: -- Internal LVD circuit and 16 bit-programmable pins for external interrupts. -- One 8-bit basic timer for oscillation stabilization and watchdog function (system reset). -- One 8-bit timer/counter and one 16-bit timer/counter with selectable operating modes. -- One 8-bit counter with auto-reload function and one-shot or repeat control. The S3C80F7/C80F9/C80G7/C80G9 is a versatile general-purpose microcontroller which is especially suitable for use as remote transmitter controller. It is currently available in a 32-pin SOP, 42-pin SDIP and 44-pin QFP package. 1-1 PRODUCT OVERVIEW S3C80F7/C80F9/C80G7/C80G9 (KS88C01524/C01532/C01624/C01632) FEATURES CPU * Carrier Frequency Generator * SAM87RC CPU core One 8-bit counter with auto-reload function and one-shot or repeat control (Counter A) Memory * * * 32-Kbyte internal ROM (S3C80F9/C80G9) : 0000H-7FFFH 24-Kbyte internal ROM (S3C80F7/C80G7) : 0000H-5FFFH Data memory: 272-byte RAM (318 register) Back-up mode * When VDD is lower than VLVD, the chip enters Back-up mode to block oscillation and reduce the current consumption. In S3C80G7/C80G9, this function is disabled when operating state is "STOP mode". Instruction Set * * * 78 instructions IDLE and STOP instructions added for powerdown modes * * When RESET pin is lower than Input Low Voltage (VIL), the chip enters Back-up mode to block oscillation and reduce the current consumption. Instruction Execution Time * Low Voltage Detect Circuit Low voltage detect to get into Back-up mode. Low level detect voltage - S3C80F7/C80F9: 2.20 V (Typ) 200mV - S3C80G7/C80G9: 1.90 V (Typ) 200mV 500 ns at 8-MHz fOSC (minimum) Interrupts * 22 interrupt sources with 16 vector and 7 level. Operating Temperature Range * I/O Ports * -40 C to + 85 C Three 8-bit I/O ports (P0-P2), one 8-bit output port(P4) and 6-bit port (P3) for a total of 38 bitprogrammable pins.(44-QFP) Three 8-bit I/O ports (P0-P2), one 8-bit output port(P4) and 4-bit port (P3) for a total of 36 bitprogrammable pins.(42-SDIP) Three 8-bit I/O ports (P0-P2) and one 2-bit I/O port (P3) for a total of 26-bit programmable pins. (32-SOP) Operating Voltage Range * * * 1.7V to 5.0V at 4 MHz fOSC (S3C80G7/C80G9) 2.0V to 5.0V at 8 MHz fOSC (S3C80F7/C80F9) * Package Type * * * 44-pin QFP-1010B 42-pin SDIP 32-pin SOP Timers and Timer/Counters * One programmable 8-bit basic timer (BT) for oscillation stabilization control or watchdog timer (software reset) function One 8-bit timer/counter (Timer 0) with three operating modes; Interval mode, Capture and PWM mode. One 16-bit timer/counter (Timer1) with two operating modes; Interval mode and Capture. * * 1-2 S3C80F7/C80F9/C80G7/C80G9 (KS88C01524/C01532/C01624/C01632) PRODUCT OVERVIEW BLOCK DIAGRAM P0.0-0.3 (INT0-INT3) P0.4-P0.7 (INT4) P1.0-P1.7 VDD LVD Port 0 Port 1 TEST RESET XIN XOUT MAIN OSC 8-Bit Basic Timer 8-Bit Timer/ Counter 16-Bit Timer/ Counter Port 2 P2.0-2.3 (INT5-INT8) P2.4-2.7 (INT9) P3.0-T0PWM/ T0CAP/(T1CAP) P3.1-REM/(T0CK) P3.2/(T0CK) P3.3/(T1CAP) P3.4-3.5 I/O Port and Interrupt Control Port 3 SAM87RC CPU Port 4 32K-Bytes ROM 317-Bytes Register File Carrier Registor (Counter A) P4.0-4.7 Figure 1-1. Block Diagram 1-3 PRODUCT OVERVIEW S3C80F7/C80F9/C80G7/C80G9 (KS88C01524/C01532/C01624/C01632) PIN ASSIGNMENTS P4.2 P4.1 P4.0 P2.0/INT5 P2.1/INT6 P2.2/INT7 P2.3/INT8 P2.4/INT9 P3.0/T0PWM/T0CAP/SDAT R3.1/REM/SCLK VDD VSS XOUT XIN TEST P2.5/INT9 P2.6/INT9 RESET P2.7/INT9 P1.0 P3.2/T0CK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 S3C80F7/C80F9 /C80G7/C80G9 (Top View) 42-SDIP 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 P4.3 P0.7/INT4 P0.6/INT4 P0.5/INT4 P0.4/INT4 P0.3/INT3 P0.2/INT2 P0.1/INT1 P0.0/INT0 P4.4 P4.5 P4.6 P1.7 P1.6 P1.5 P1.4 P1.3 P1.2 P1.1 P4.7 P3.3/T1CAP Figure 1-2. Pin Assignment Diagram (42-Pin SDIP Package) 1-4 S3C80F7/C80F9/C80G7/C80G9 (KS88C01524/C01532/C01624/C01632) PRODUCT OVERVIEW 33 32 31 30 29 28 27 26 25 24 23 P0.3/INT3 P0.2/INT2 P0.1/INT1 P0.0/INT0 P4.4 P4.5 P4.6 P1.7 P1.6 P1.5 P1.4 P0.4/INT4 P0.5/INT4 P0.6/INT4 P0.7/INT4 P4.3 P4.2 P4.1 P4.0 P2.0/INT5 P2.1/INT6 P2.2/INT7 34 35 36 37 38 39 40 41 42 43 44 S3C80F7/C80F9 /C80G7/C80G9 (Top View) (44-QFP) 1 2 3 4 5 6 7 8 9 10 11 22 21 20 19 18 17 16 15 14 13 12 P1.3 P1.2 P1.1 P4.7 P3.3/T1CAP P3.2/T0CK P1.0 P2.7/INT9 P3.5 P3.4 RESET Figure 1-3. Pin Assignment Diagram (44-Pin QFP Package) P2.3/INT8 P2.4/INT9 P3.0/T0PWM/T0CAP/SDAT P3.1/REM/SCLK VDD VSS XOUT XIN TEST P2.5/INT9 P2.6/INT9 1-5 PRODUCT OVERVIEW S3C80F7/C80F9/C80G7/C80G9 (KS88C01524/C01532/C01624/C01632) VSS XIN XOUT TEST P2.5/INT9 P2.6/INT9 RESET P2.7/INT9 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 S3C80F7/C80F9 /C80G7/C80G9 (Top View) 32-SOP 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VDD P3.1/REM/T0CK/SCLK P3.0/T0PWM/T0CAP/T1CAP/SDAT P2.4/INT9 P2.3/INT8 P2.2/INT7 P2.1/INT6 P2.0/INT5 P0.7/INT4 P0.6/INT4 P0.5/INT4 P0.4/INT4 P0.3/INT3 P0.2/INT2 P0.1/INT1 P0.0/INT0 Figure 1-4. Pin Assignment Diagram (32-Pin SOP Package) 1-6 S3C80F7/C80F9/C80G7/C80G9 (KS88C01524/C01532/C01624/C01632) PRODUCT OVERVIEW Table 1-1. Pin Descriptions of 44-QFP and 42-SDIP Pin Names P0.0-P0.7 Pin Type I/O Pin Description I/O port with bit-programmable pins. Configurable to input or push-pull output mode. Pull-up resistors can be assigned by software. Pins can be assigned individually as external interrupt inputs with noise filters, interrupt enable/ disable, and interrupt pending control. SED & R circuit built in P0 for STOP releasing. I/O port with bit-programmable pins. Configurable to input mode or output mode. Pin circuits are either push-pull or n-channel open-drain type. I/O port with bit-programmable pins. Configurable to input or push-pull output mode. Pull-up resistors can be assigned by software. Pins can be assigned individually as external interrupt inputs with noise filters, interrupt enable/ disable, and interrupt pending control. SED & R circuit built in P2 for STOP releasing. 2-bit I/O port with bit-programmable pins. Configurable to input mode, push-pull output mode, or n-channel open-drain output mode. Input mode with pull-up resistors can be assigned by software. The two port 3 pins have high current drive capability C-MOS Input port with pull-up resistors Open drain output port for high current drive 8- bit-programmable output pins. Configurable to open drain output port or push-pull output port. System clock input and output pins System reset signal input pin and backup mode input. Test signal input pin (for factory use only; must be connected to VSS.) Power supply input pin Ground pin Circuit Type 1 42 Pin No. 34-41 44 Pin No. 30-37 Shared Functions Ext. INT (INT0 - 4) P1.0-P1.7 I/O 2 20 24-30 16 20-26 - P2.0-P2.3 P2.4-P2.7 I/O 1 4-8, 16, 17 19 42-44 1,2, 10,11, 15 Ext. INT (INT5-9) P3.0 P3.1 I/O 3 4 9-10 3-4 T0PWM/ T0CAP REM P3.2-P3.3 P3.4-P3.5 P4.0-P4.7 I O O 5 6 7 21 22 None 1-3 42,23 31-33 13,14 18 15 11 12 17 18 13-14 41-38 27-29 19 7,8 12 9 5 6 (T0CK) (T1CAP) - - XIN, XOUT RESET - I I - - - 8 - - - - - - - - TEST VDD VSS 1-7 PRODUCT OVERVIEW S3C80F7/C80F9/C80G7/C80G9 (KS88C01524/C01532/C01624/C01632) Table 1-2. Pin Descriptions of 32-SOP Pin Names P0.0-P0.7 Pin Type I/O Pin Description I/O port with bit-programmable pins. Configurable to input or push-pull output mode. Pull-up resistors are assignable by software. Pins can be assigned individually as external interrupt inputs with noise filters, interrupt enable/ disable, and interrupt pending control. SED & R circuit built in P0 for STOP releasing. I/O port with bit-programmable pins. Configurable to input mode or output mode. Pin circuits are either push-pull or n-channel open-drain type. I/O port with bit-programmable pins. Configurable to input or push-pull output mode. Pull-up resistors can be assigned by software. Pins can be assigned individually as external interrupt inputs with noise filters, interrupt enable/disable, and interrupt pending control. SED & R circuit built in P2 for STOP releasing. 2-bit I/O port with bit-programmable pins. Configurable to input mode, push-pull output mode, or n-channel open-drain output mode. Input mode with pull-up resistors can be assigned by software. The two port 3 pins have high current drive capability. System clock input and output pins System reset signal input pin and back-up mode input. Test signal input pin (for factory use only; must be connected to VSS). VDD VSS - - Power supply input pin Ground pin - - 32 1 - - Circuit Type 1 32 Pin No. 17-24 Shared Functions Ext. INT P1.0-P1.7 I/O 2 9-16 - P2.0-P2.3 P2.4-P2.7 I/O 1 25-28 29,5, 6,8 Ext. INT P3.0 P3.1 I/O 3 4 30,31 T0PWM/ T0CAP/T1CAP REM/T0CK XIN, XOUT RESET - I I - 8 - 2,3 7 4 - - - TEST 1-8 S3C80F7/C80F9/C80G7/C80G9 (KS88C01524/C01532/C01624/C01632) PRODUCT OVERVIEW PIN CIRCUITS VDD Pull-up Resistor Pull-up Enable VDD Data Input/ Output Output Disable VSS External Interrupt Noise Filter Stop Stop release Figure 1-5. Pin Circuit Type 1 (Port 0 and Port2) 1-9 PRODUCT OVERVIEW S3C80F7/C80F9/C80G7/C80G9 (KS88C01524/C01532/C01624/C01632) PIN CIRCUITS (Continued) VDD Pull-up Resistor Pull-up Enable VDD Data Input/ Output Open-Drain Output Disable VSS Normal Input Noise Filter Figure 1-6. Pin Circuit Type 2 (Port 1) 1-10 S3C80F7/C80F9/C80G7/C80G9 (KS88C01524/C01532/C01624/C01632) PRODUCT OVERVIEW PIN CIRCUITS (Continued) VDD Pull-up Resistor Pull-up Enable P3CON.2 VDD Port 3.0 Data T0_PWM M U X Data Open-Drain Output Disable VSS P3.0 Input P3CON.2,6,7 M U X P3.0/T0PWM T0CAP/(T1CAP) T0CAP/(T1CAP) Noise filter Figure 1-7. Pin Circuit Type 3 (P3.0) 1-11 PRODUCT OVERVIEW S3C80F7/C80F9/C80G7/C80G9 (KS88C01524/C01532/C01624/C01632) PIN CIRCUITS (Continued) VDD Pull-up Resistor Pull-up Enable P3CON.5 VDD Port 3.1 Data CAOF(CACON.0) Carrier On/Off (P3.7) M U X Data Open-Drain Output Disable VSS P3.1 Input P3CON.5,6,7 M U X P3.1/REM/(T0CK) T0CK Noise filter Figure 1-8. Pin Circuit Type 4 (P3.1) Circuit VDD Pull-up Resistor Input T0CK : P3.2 T1CAP: P3.3 M U X Figure 1-9. Pin Circuit Type 5 (P3.2, P3.3) 1-12 S3C80F7/C80F9/C80G7/C80G9 (KS88C01524/C01532/C01624/C01632) PRODUCT OVERVIEW PIN CIRCUITS (Continued) Output Data VSS Figure 1-10. Pin Circuit type 6 (P3.4, P3.5) VDD Data Output Open-Drain Output Disable VSS Figure 1-11. Pin Circuit type 7 (Port 4) VDD Pull-up Resistor RESET Figure 1-12. Pin Circuit type 8 (RESET) 1-13 S3C80F7/C80F9/C80G7/C80G9 (KS88C01524/C01532/C01624/C01632) ELECTRICAL DATA 14 OVERVIEW ELECTRICAL DATA 1 (S3C80F7/C80F9) In this section, S3C80F7/C80F9 electrical characteristics are presented in tables and graphs. The information is arranged in the following order: -- Absolute maximum ratings -- D.C. electrical characteristics -- Data retention supply voltage in Stop mode -- Stop mode release timing when initiated by an external interrupt -- Stop mode release timing when initiated by a Reset -- I/O capacitance -- A.C. electrical characteristics -- Input timing for external interrupts -- Input timing for RESET -- Oscillation characteristics -- Oscillation stabilization time 14-1 ELECTRICAL DATA S3C80F7/C80F9/C80G7/C80G9 (KS88C01524/C01532/C01624/C01632) Table 14-1. Absolute Maximum Ratings (TA = 25 C) Parameter Supply voltage Input voltage Output voltage Output current High Symbol VDD VIN VO I OH I OL All output pins One I/O pin active All I/O pins active Output current Low One I/O pin active Total pin current for ports 0, 1, and 2 Total pin current for port 3 Operating temperature Storage temperature TA TSTG - - Conditions - - Rating - 0.3 to + 6.5 - 0.3 to VDD + 0.3 - 0.3 to VDD + 0.3 - 18 - 60 + 30 + 100 + 40 - 40 to + 85 - 65 to + 150 C C mA Unit V V V mA Table 14-2. D.C. Electrical Characteristics (TA = - 40 C to + 85 C, VDD = 2.0 V to 5.0 V) Parameter Operating Voltage Input High voltage Symbol VDD VIH1 VIH2 VIH3 Input Low voltage VIL1 VIL2 VIL3 Output High voltage VOH1 VOH2 Conditions FOSC = 8 MHz (Instruction clock = 2 MHz) All input pins except VIH2 and VIH3 RESET Min 2.0 0.8 VDD 0.85 VDD VDD - 0.3 0 Typ - - Max 5.0 VDD VDD VDD Unit V V XIN All input pins except VIL2 and VIL3 RESET - 0.2 VDD 0.2 VDD 0.3 V XIN VDD = 2.4 V IOH = - 6 mA Port 3.1 only, TA = 25C VDD = 2.4 V, IOH = - 2.2mA P3.0, P2.0-2.3 TA = 25C VDD - 0.7 VDD - 0.7 V 14-2 S3C80F7/C80F9/C80G7/C80G9 (KS88C01524/C01532/C01624/C01632) ELECTRICAL DATA Table 14-2. D.C. Electrical Characteristics (Continued) (TA = - 40 C to + 85 C, VDD = 2.0 V to 5.0 V) Parameter Output High voltage Symbol VOH3 Conditions VDD = 2.4 V,IOH = - 1 mA Port0, Port1, P2.4-2.7 and Port4 TA = 25C 3.1 only, TA = 25C VDD = 2.4 V, IOL = 12 mA, port VDD = 2.4 V, IOL = 5 mA P3.0, P3.4-3.5, P2.0-2.3 TA = 25C IOL = 2mA Port 0, Port1, P2.4-2.7 and Port4 TA = 25C VIN = VDD All input pins except XIN and XOUT VIN = VDD, XIN and XOUT VIN = 0 V All input pins except XIN, XOUT, and RESET VIN = 0 V XIN and XOUT VOUT = VDD All output pins VOUT = 0 V All output pins VIN = 0 V, VDD = 2.4 V TA = 25C, Ports 0-2, P3.2-3.3 - - 44 - - 55 - - - Min VDD - 1.0 Typ - Max - Unit V Output Low voltage VOL1 VOL2 - 0.4 0.4 0.5 0.5 V VOL3 0.4 1 Input High leakage current ILIH1 - 1 A ILIH2 Input Low leakage current ILIL1 20 -1 A ILIL2 Output High leakage current Output Low leakage current Pull-up resistors ILOH ILOL RL1 - 20 1 -1 95 A A k 14-3 ELECTRICAL DATA S3C80F7/C80F9/C80G7/C80G9 (KS88C01524/C01532/C01624/C01632) Table 14-2. D.C. Electrical Characteristics (Continued) (TA = - 40 C to + 85 C, VDD = 2.0 V to 5.0 V) Parameter Supply current (note) Symbol IDD1 Conditions Operating mode VDD = 5.0 V 8 MHz crystal 4 MHz crystal Min - Typ 6 Max 11 Unit mA 4.5 1.8 9 3.5 IDD2 Idle mode VDD = 5.0 V 8 MHz crystal 4 MHz crystal Stop mode; VDD = 5.0 V VDD = 3.6 V VDD = 2.4 V VDD = 0.7 V - 1.6 18 12 4.5 1 3.0 25 15 8 1.5 uA IDD3 NOTE: Supply current does not include current drawn through internal pull-up resistors or external output current loads. Table 14-3. Characteristics of Low Voltage Detect circuit (TA = - 40 C to + 85 C) Parameter Hysteresys Voltage of LVD (Slew Rate of LVD) Low level detect voltage Symbol V VLVD Conditions - - Min - 2.00 Typ 100 2.20 Max 300 2.40 Unit mV V Table 14-4. Data Retention Supply Voltage in Stop Mode (TA = - 40 C to + 85 C) Parameter Data retention supply voltage Data retention supply current Symbol VDDDR IDDDR Conditions - VDDDR = 1.0 V Stop mode Min 1.0 - Typ - - Max 5.0 1 Unit V A 14-4 S3C80F7/C80F9/C80G7/C80G9 (KS88C01524/C01532/C01624/C01632) ELECTRICAL DATA Stop Mode Data Retention Mode Idle Mode (Basic Timer Active) ~ ~ ~ ~ VDD VDDDR Execution of STOP Instrction EXT INT 0.2VDD 0.8VDD tWAIT Normal Operating Mode Figure 14-1. Stop Mode Release Timing When Initiated by an External Interrupt Reset Occur Stop Mode Oscillation Stabilization Time Normal Operating Mode ~ ~ VDD Execution of STOP Instrction RESET ~ ~ tWAIT NOTE: tWAIT is the same as 4096 x 16 x 1/fOSC. Figure 14-2. Stop Mode Release Timing When Initiated by a RESET 14-5 ELECTRICAL DATA S3C80F7/C80F9/C80G7/C80G9 (KS88C01524/C01532/C01624/C01632) Reset Occur Stop Mode Oscillation Stabilization Time Normal Operating Mode Back-up Mode ~ ~ VDD VLVD Execution of STOP Instrction NOTE: tWAIT is the same as 4096 x 16 x 1/fOSC. Figure 14-3. Stop Mode Release Timing When Initiated by a LVD (TA = - 40 C to + 85 C , VDD = 0 V) Parameter Input capacitance Output capacitance I/O capacitance Symbol CIN COUT CIO Conditions f = 1 MHz; unmeasured pins are connected to VSS Min - Typ - Max 10 Unit pF ~ ~ VDDDR tWAIT Data Retention Time Table 14-5. Input/Output Capacitance Table 14-6. A.C. Electrical Characteristics (TA = - 40 C to + 85 C) Parameter Interrupt input, High, Low width RESET input Low Symbol tINTH, tINTL tRSL Conditions P0.0-P0.7, P2.3-P2.0 VDD = 5.0 V Input VDD = 5.0 V Min 200 1000 Typ 300 - Max - - Unit ns width 14-6 S3C80F7/C80F9/C80G7/C80G9 (KS88C01524/C01532/C01624/C01632) ELECTRICAL DATA tINTL tINTH 0.8 VDD 0.2 VDD NOTE: The unit tCPU means one CPU clock period. Figure 14-4. Input Timing for External Interrupts (Port 0, P2.3-P2.0) Reset Occur Normal Operating Mode VDD Back-up Mode (Stop Mode) Oscillation Stabilization Time Normal Operating Mode RESET tWAIT NOTE: tWAIT is the same as 4096 x 16 x 1/fOSC. Figure 14-5. Input Timing for RESET 14-7 ELECTRICAL DATA S3C80F7/C80F9/C80G7/C80G9 (KS88C01524/C01532/C01624/C01632) Table 14-7. Oscillation Characteristics (TA = - 40 C + 85 C) Oscillator Crystal XIN C1 XOUT C2 Clock Circuit Conditions CPU clock oscillation frequency Min 1 Typ - Max 8 Unit MHz Ceramic XIN C1 XOUT C2 CPU clock oscillation frequency 1 - 8 MHz External clock External Clock Open Pin XIN S3C80F9 XIN input frequency 1 - 8 MHz XOUT Table 14-8. Oscillation Stabilization Time (TA = - 40 C + 85 C, VDD = 4.5 V to 5.0 V) Oscillator Main crystal Main ceramic External clock (main system) Oscillator stabilization wait time Test Condition f OSC > 400 kHz Oscillation stabilization occurs when VDD is equal to the minimum oscillator voltage range. XIN input High and Low width (tXH, tXL) tWAIT when released by a reset (1) (2) Min - - 25 - Typ - - - 2 /fOSC 16 Max 20 10 500 - Unit ms ms ns ms tWAIT when released by an interrupt - - - ms NOTES: 1. fOSC is the oscillator frequency. 2. The duration of the oscillation stabilization time (tWAIT) when it is released by an interrupt is determined by the setting in the basic timer control register, BTCON. 14-8 S3C80F7/C80F9/C80G7/C80G9 (KS88C01524/C01532/C01624/C01632) ELECTRICAL DATA Instruction Clock 2 MHz 1.25 MHz 1.0 MHz 500 kHz 250 kHz 100 kHz 1 2 3 4 5 6 7 A fOSC (Main Oscillator Frequency) 8 MHz 6 MHz 4 MHz 400 kHz Supply Voltage (V) Instruction Clock = 1/6n x oscillator frequency (n = 1, 2, 8, or 16) A: 2.0 V, 8 MHz Figure 14-6. Operating Voltage Range of S3C80F9 14-9 S3C80F7/C80F9/C80G7/C80G9 (KS88C01524/C01532/C01624/C01632) ELECTRICAL DATA 15 OVERVIEW ELECTRICAL DATA 2 (S3C80G7/C80G9) In this section, S3C80G7/C80G9 electrical characteristics are presented in tables and graphs. The information is arranged in the following order: -- Absolute maximum ratings -- D.C. electrical characteristics -- Data retention supply voltage in Stop mode -- Stop mode release timing when initiated by an external interrupt -- Stop mode release timing when initiated by a Reset -- I/O capacitance -- A.C. electrical characteristics -- Input timing for external interrupts -- Input timing for RESET -- Oscillation characteristics -- Oscillation stabilization time 15-1 ELECTRICAL DATA S3C80F7/C80F9/C80G7/C80G9 (KS88C01524/C01532/C01624/C01632) Table 15-1. Absolute Maximum Ratings (TA = 25 C) Parameter Supply voltage Input voltage Output voltage Output current High Symbol VDD VIN VO I OH I OL All output pins One I/O pin active All I/O pins active Output current Low One I/O pin active Total pin current for ports 0, 1, and 2 Total pin current for port 3 Operating temperature Storage temperature TA TSTG - - Conditions - - Rating - 0.3 to + 6.5 - 0.3 to VDD + 0.3 - 0.3 to VDD + 0.3 - 18 - 60 + 30 + 100 + 40 - 40 to + 85 - 65 to + 150 C C mA Unit V V V mA Table 15-2. D.C. Electrical Characteristics (TA = - 40 C to + 85 C, VDD = 2.0 V to 5.0 V) Parameter Operating Voltage Input High voltage Symbol VDD VIH1 VIH2 VIH3 Input Low voltage VIL1 VIL2 VIL3 Output High voltage VOH1 VOH2 Conditions FOSC = 4 MHz (Instruction clock = 1 MHz) All input pins except VIH2 and VIH3 RESET Min 1.7 0.8 VDD 0.85 VDD VDD - 0.3 0 Typ - - Max 5.0 VDD VDD VDD Unit V V XIN All input pins except VIL2 and VIL3 RESET - 0.2 VDD 0.2 VDD 0.3 V XIN VDD = 2.4 V IOH = - 6 mA Port 3.1 only, TA = 25C VDD = 2.4 V, IOH = - 2.2mA P3.0, P2.0-2.3 TA = 25C VDD - 0.7 VDD- 0.7 V 15-2 S3C80F7/C80F9/C80G7/C80G9 (KS88C01524/C01532/C01624/C01632) ELECTRICAL DATA Table 15-2. D.C. Electrical Characteristics (Continued) (TA = - 40 C to + 85 C, VDD = 2.0 V to 5.0 V) Parameter Output High voltage Symbol VOH3 Conditions VDD = 2.4 V,IOH = - 1 mA Port0, Port1, P2.4-2.7 and Port4 TA = 25C Output Low voltage VOL1 VOL2 3.1 only, TA = 25C VDD = 2.4 V, IOL = 12 mA, port VDD = 2.4 V, IOL = 5 mA P3.0, P3.4-3.5, P2.0-2.3 TA = 25C IOL = 2mA Port 0, Port1, P2.4-2.7 and Port4 TA = 25C Input High leakage current ILIH1 VIN = VDD All input pins except XIN and XOUT VIN = VDD, XIN and XOUT VIN = 0 V All input pins except XIN, XOUT, and RESET VIN = 0 V XIN and XOUT VOUT = VDD All output pins VOUT = 0 V All output pins VIN = 0 V, VDD = 2.4 V TA = 25C, Ports 0-2, P3.2-3.3 - - 44 - - 55 - - - - 1 A - 0.4 0.4 0.5 0.5 V Min VDD - 1.0 Typ - Max - Unit V VOL3 0.4 1 ILIH2 Input Low leakage current ILIL1 20 -1 A ILIL2 Output High leakage current Output Low leakage current Pull-up resistors ILOH ILOL RL1 - 20 1 -1 95 A A k 15-3 ELECTRICAL DATA S3C80F7/C80F9/C80G7/C80G9 (KS88C01524/C01532/C01624/C01632) Table 15-2. D.C. Electrical Characteristics (Continued) (TA = - 40 C to + 85 C, VDD = 2.0 V to 5.0 V) Parameter Supply current (note) Symbol IDD1 Conditions Operating mode VDD = 5.0 V 4 MHz crystal Idle mode VDD = 5.0 V 4 MHz crystal Stop mode; VDD = 5.0 V Min - Typ 4.5 Max 9 Unit mA IDD2 1.6 3.0 IDD3 - 1 6 uA NOTE: Supply current does not include current drawn through internal pull-up resistors or external output current loads. Table 15-3. Characteristics of Low Voltage Detect circuit (TA = - 40 C to + 85 C) Parameter Hysteresys Voltage of LVD (Slew Rate of LVD) Low level detect voltage Symbol V VLVD Conditions - - Min - 1.70 Typ 100 1.90 Max 300 2.10 Unit mV V Table 15-4. Data Retention Supply Voltage in Stop Mode (TA = - 40 C to + 85 C) Parameter Data retention supply voltage Data retention supply current Symbol VDDDR IDDDR Conditions - VDDDR = 1.0 V Stop mode Min 1.0 - Typ - - Max 5.0 1 Unit V A 15-4 S3C80F7/C80F9/C80G7/C80G9 (KS88C01524/C01532/C01624/C01632) ELECTRICAL DATA Stop Mode Data Retention Mode Idle Mode (Basic Timer Active) ~ ~ ~ ~ VDD VDDDR Execution of STOP Instrction EXT INT 0.2VDD 0.8VDD tWAIT Normal Operating Mode Figure 15-1. Stop Mode Release Timing When Initiated by an External Interrupt Reset Occur Stop Mode Oscillation Stabilization Time Normal Operating Mode ~ ~ VDD Execution of STOP Instrction RESET ~ ~ tWAIT NOTE: tWAIT is the same as 4096 x 16 x 1/fOSC. Figure 15-2. Stop Mode Release Timing When Initiated by a RESET 15-5 ELECTRICAL DATA S3C80F7/C80F9/C80G7/C80G9 (KS88C01524/C01532/C01624/C01632) Table 15-5. Input/Output Capacitance (TA = - 40 C to + 85 C , VDD = 0 V) Parameter Input capacitance Output capacitance I/O capacitance Symbol CIN COUT CIO Conditions f = 1 MHz; unmeasured pins are connected to VSS Min - Typ - Max 10 Unit pF Table 15-6. A.C. Electrical Characteristics (TA = - 40 C to + 85 C) Parameter Interrupt input, High, Low width RESET input Low Symbol tINTH, tINTL tRSL Conditions P0.0-P0.7, P2.3-P2.0 VDD = 5.0 V Input VDD = 5.0 V Min 200 1000 Typ 300 - Max - - Unit ns width 15-6 S3C80F7/C80F9/C80G7/C80G9 (KS88C01524/C01532/C01624/C01632) ELECTRICAL DATA tINTL tINTH 0.8 VDD 0.2 VDD NOTE: The unit tCPU means one CPU clock period. Figure 15-3. Input Timing for External Interrupts (Port 0, P2.3-P2.0) Reset Occur Normal Operating Mode VDD Back-up Mode (Stop Mode) Oscillation Stabilization Time Normal Operating Mode RESET tWAIT NOTE: tWAIT is the same as 4096 x 16 x 1/fOSC. Figure 15-4. Input Timing for RESET 15-7 ELECTRICAL DATA S3C80F7/C80F9/C80G7/C80G9 (KS88C01524/C01532/C01624/C01632) Table 15-7. Oscillation Characteristics (TA = - 40 C + 85 C) Oscillator Crystal XIN C1 XOUT C2 Clock Circuit Conditions CPU clock oscillation frequency Min 1 Typ - Max 4 Unit MHz Ceramic XIN C1 XOUT C2 CPU clock oscillation frequency 1 - 4 MHz External clock External Clock Open Pin XIN S3C80G9 XIN input frequency 1 - 4 MHz XOUT Table 15-8. Oscillation Stabilization Time (TA = - 40 C + 85 C, VDD = 4.5 V to 5.0 V) Oscillator Main crystal Main ceramic External clock (main system) Oscillator stabilization wait time Test Condition f OSC > 400 kHz Oscillation stabilization occurs when VDD is equal to the minimum oscillator voltage range. XIN input High and Low width (tXH, tXL) tWAIT when released by a reset (1) tWAIT when released by an interrupt (2) Min - - 25 - 16 Typ - - - 2 /fOSC Max 20 10 500 - Unit ms ms ns ms - - - ms NOTES: 1. fOSC is the oscillator frequency. 2. The duration of the oscillation stabilization time (tWAIT) when it is released by an interrupt is determined by the setting in the basic timer control register, BTCON. 15-8 S3C80F7/C80F9/C80G7/C80G9 (KS88C01524/C01532/C01624/C01632) ELECTRICAL DATA Instruction Clock 2 MHz 1.25 MHz 1.0 MHz 500 kHz 250 kHz 100 kHz 1 2 3 4 5 6 7 A fOSC (Main Oscillator Frequency) 8 MHz 6 MHz 4 MHz 400 kHz Supply Voltage (V) Instruction Clock = 1/6n x oscillator frequency (n = 1, 2, 8, or 16) A: 1.7 V, 4 MHz Figure 15-6. Operating Voltage Range of S3C80G9 15-9 S3C80F7/C80F9/C80G7/C80G9 (KS88C01524/C01532/C01624/C01632) MECHANICAL DATA 16 OVERVIEW #32 MECHANICAL DATA The S3C80F7/C80F9/C80G7/C80G9 microcontroller is currently available in a 32-pin SOP, 42-pin SDIP and 44pin QFP package. 0-8 #17 12.00 0.30 0.20 32-SOP-450A 8.34 0.25 0.10 20.30 MAX 19.90 0.20 2.20 MAX 2.00 0.10 MAX (0.43) 0.40 0.10 1.27 NOTE: Dimensions are in millimeters. Figure 16-1. 32-Pin SOP Package Dimension 0.05 MIN 0.90 0.20 #1 #16 + 0.10 - 0.05 11.43 16-1 MECHANICAL DATA S3C80F7/C80F9/C80G7/C80G9 (KS88C01524/C01532/C01624/C01632) #42 #22 0-15 14.00 0.20 #1 #21 3.50 0.20 39.50 MAX 39.10 0.20 0.50 0.10 (1.77) 1.00 0.10 1.78 NOTE: Dimensions are in millimeters. Figure 16-2. 42-Pin SDIP Package Dimension 16-2 3.30 0.30 0.51 MIN 5.08 MAX 0.2 5 +0 - 0 .10 .05 42-SDIP-600 15.24 S3C80F7/C80F9/C80G7/C80G9 (KS88C01524/C01532/C01624/C01632) MECHANICAL DATA 13.20 0.30 0-8 10.00 0.20 0.15 + 0.10 - 0.05 13.20 0.30 10.00 0.20 44-QFP-1010B 0.80 0.20 #1 0.80 + 0.10 0.10 MAX #44 0.35 - 0.05 0.15 MAX (1.00) 0.05 MIN 2.05 0.10 2.30 MAX NOTE: Dimensions are in millimeters. Figure 16-3. 44-Pin SQFP Package Dimension 16-3 |
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